Open to full-time DV/RTL roles
Aspiring ASIC Design Verification Engineer · Brooklyn, NY
Featured · Design verification
A UVM testbench strict enough to catch three real RTL bugs, each reproducible with its own failing test.
Clock domain crossing
A parameterized async FIFO checked by a bind-attached assertion suite across five write/read clock ratios.
AI for verification
Grounded answers from the 500-page ARM AXI4 spec, plus an agent that turns coverage holes into UVM stimulus ideas.
Protocol verification
Self-checking SPI scoreboard validating CPOL/CPHA modes against a reference memory model.
I explain digital design and verification concepts on YouTube, worked through step by step from first principles.
Latest · SystemVerilog
A 15-minute explainer on what a simulator does inside one moment of simulation time. It walks through the 9 scheduling regions step by step, showing where race conditions come from and how nonblocking assignments, $strobe, clocking blocks and deferred assertions avoid them. Every result is checked against a model of the IEEE 1800-2023 scheduler.
Verification sign-off
Testing can never prove a chip has no bugs, so how does a DV team decide it’s done? Covers the verification plan, code vs functional coverage, three ways to close a coverage hole, mutation testing, bug-rate curves and the sign-off review, with a simulated FIFO bug as the running example.
Verification case study
A design verification case study of the Pentium FDIV bug, built on my own bit-level model of its SRT divider: why 1,000,000 random tests never touched the 5 defective table cells, and how coverage and formal proofs catch bugs like it.
Interview prep
One idea answers every version of “how deep must this FIFO be?”: it only has to hold the backlog that builds while writes outpace reads. It solves the standard case, then works through eight traps, from idle cycles and the 2X trap to back-to-back bursts and async margin.
Clock domain crossing
Builds an asynchronous FIFO step by step to show how data crosses safely between two unrelated clocks: the lap bit, metastability and the two-flop synchronizer, why a binary pointer going from 7 to 8 can arrive as 15, and how Gray code fixes it.
Reliability & ECC
A 2003 Belgian election gave one candidate exactly 4,096 extra votes: 212, a single flipped bit. What a bit flip is, how chips survive one with parity and ECC, and how verification engineers use fault injection to prove every flip gets fixed or caught.
I recently completed my MS in Computer Engineering at NYU Tandon. I specialize in ASIC Design Verification — UVM, SystemVerilog, and constrained-random verification across industry-standard protocols — and I build LLM/RAG tooling on top of that workflow to cut down manual toil in spec lookup, stimulus generation, and coverage closure.
I also explain digital design and verification concepts on YouTube — from FIFO sizing and clock domain crossing to ECC, the Pentium FDIV bug and how SystemVerilog schedules events.
UVM testbenches with constrained-random stimulus, self-checking scoreboards and reference models, driven to coverage closure.
Protocol rules, clock domain crossings and corner cases, pinned down with SVA so a bug can't slip through quietly.
Scripts and LLM tooling that take over the repetitive parts: regressions, grading pipelines, spec lookup and coverage analysis.
Turning tricky hardware concepts into explanations people remember, on YouTube and in the lab as a course assistant.
2020 – 2024
College of Engineering Guindy, Anna University · CGPA 8.51/10
Digital System Design, Digital VLSI, Linear ICs, Operating Systems, Machine Learning, Advanced Microcontrollers.
2024 – 2026
NYU Tandon School of Engineering · CGPA 3.87/4.0
Generative AI Based Chip Design, SoC Design, Computing Systems Architecture, VLSI Systems & Architecture.
Jun 2025 – May 2026
New York University
Automated a Python grading pipeline that batch-compiles and simulates student RTL in Synopsys VCS; wrote lab manuals and debugged student RTL and testbenches during lab hours.
Now
Looking for ASIC design verification and RTL roles. Get in touch.